【博士論文】学術データベース

博士論文 / Unified Hardware/Software Co-verification Framework for Large Scale Systems 大規模システムLSI設計のための統一的ハードウェア・ソフトウェア協調検証手法

著者

書誌事項

タイトル

Unified Hardware/Software Co-verification Framework for Large Scale Systems

タイトル別名

大規模システムLSI設計のための統一的ハードウェア・ソフトウェア協調検証手法

著者名

Nana Sutisna

学位授与大学

九州工業大学 (大学ID:0071) (CAT機関ID:KI000844)

取得学位

博士(情報工学)

学位授与番号

甲情工第328号

学位授与年月日

2017-06-30

注記・抄録

Currently, the complexity of embedded LSI system is growing faster than the productivity of system design. This trend results in a design productivity gap, particularly in tight development time. Since the verification task takes bigger part of development task, it becomes a major challenge in LSI system design. In order to guarantee system reliability and quality of results (QoR), verifying large coverage of system functionality requires huge amount of relevant test cases and various scenario of evaluations. To overcome these problems, verification methodology is evolving toward supporting higher level of design abstraction by employing HW-SW co-verification. In this study, we present a novel approach for verification LSI circuit which is called as unified HW/SW co-verification framework. The study aims to improve design efficiency while maintains implementation consistency in the point of view of system-level performance. The proposed data-driven simulation and flexible interface of HW and SW design become the backbone of verification framework. In order to avoid time consuming, prone error, and iterative design spin-off in a large team, the proposed framework has to support multiple design abstractions. Hence, it can close the loop of design, exploration, optimization, and testing. Furthermore, the proposed methodology is also able to co-operate with system-level simulation in high-level abstraction, which is easy to extend for various applications and enables fast-turn around design modification. These contributions are discussed in chapter 3. In order to show the effectiveness and the use-cases of the proposed verification framework, the evaluation and metrics assessments of Very High Throughput wireless LAN system design are carried out. Two application examples are provided. The first case in chapter 4 is intended for fast verification and design exploration of large circuit. The Maximum Likelihood Detection (MLD) MIMO decoder is considered as Design Under Test (DUT). The second case, as presented in chapter 5, is the evaluation for system-level simulation. The full transceiver system based on IEEE 802.11ac standard is employed as DUT. Experimental results show that the proposed verification approach gives significant improvements of verification time (e.g. up to 10,000 times) over the conventional scheme. The proposed framework is also able to support various schemes of system level evaluations and cross-layer evaluation of wireless system.

九州工業大学博士学位論文 学位記番号:情工博甲第328号 学位授与年月日:平成29年6月30日

1 Introduction|2 Design and Verification in LSI System Design|3 Unified HW/SW Co-verification Methodology|4 Fast Co-verification and Design Exploration in Complex Circuits|5 Unified System Level Simulator for Very High Throughput Wireless Systems|6 Conclusion and Future Work

平成29年度

九州工業大学博士学位論文(要旨)学位記番号:情工博甲第328号 学位授与年月日:平成29年6月30日

キーワード

LSI Design Methodology, Unified HW/SW Co-verification, System Level Simulation, Hardware-In-the Loop, Wireless System

各種コード

NII論文ID(NAID)

500001039661

NII著者ID(NRID)
  • 8000001150753
本文言語コード

eng

データ提供元

機関リポジトリ / NDLデジタルコレクション

外部リンク

博士論文 / 九州工業大学 / 情報工学

博士論文 / 九州工業大学

博士論文 / 情報工学

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